17. CPU Exceptions
The TLB refill vector selection is based on the address space of the address (user, supervisor, or kernel) that caused the TLB miss, and the value of the corresponding extended addressing bit in the Status register (UX, SX, or KX). The current operating mode of the processor is not important except that it plays a part in specifying in which address space an address resides. The Context and XContext registers are entirely separate page-table-pointer registers that point to and refill from two separate page tables, however these two registers share BadVPN2 fields (see Chapter 14 for more information). For all TLB exceptions (Refill, Invalid, TLBL or TLBS), the BadVPN2 fields of both registers are loaded as they were in the R4400.
In contrast to the R10000, the R4400 processor selects the vector based on the current operating mode of the processor (user, supervisor, or kernel) and the value of the corresponding extended addressing bit in the Status register (UX, SX or KX). In addition, the Context and XContext registers are not implemented as entirely separate registers; the PTEbase fields are shared. A miss to a particular address goes through either TLB Refill or XTLB Refill, depending on the source of the reference. There can be only be a single page table unless the refill handlers execute address-deciphering and page table selection in software.
